1. Field of the Invention
The present invention relates to a memory controller.
2. Description of the Prior Art
A resource sharing system, which includes more than one resource and a plurality of resource access means sharing the resources, for competing accesses among the resource access means has been known. In such a resource sharing system, the optimum priority order of the system is to be dynamically changed but the priority order to resolve access competition is fixed. Accordingly, the throughput of an overall system is not improved. Where the frequency of access to the resources by one resource access means is low but its priority order is high, permission of access to the resources by the access means having a high frequency of access is postponed.
More specifically, the access competition in a memory circuit comprising a dynamic ram (DRAM) (DRAM is a resource) will now be explained.
FIG. 3 is a block diagram of a prior art memory control circuit of the DRAM. Numeral 107 denotes a crystal (XTAL) which supplies a basic clock of the DRAM control circuit to a timing generator 108. The timing generator 108 periodically generates a request sampling signal (RQSPL) by which logical states such as refresh request (REFRQ), write request (WRRQ) and read request (RDRQ) are latched into flip-flops (FF) 101, 102 and 103, respectively. (Those operations are called request sampling). In the prior art circuit of FIG. 3, the priority order is fixed to the order of REFRQ, WRRQ, RDRQ. The refresh request REFRQ has the highest priority. If this request is sampled, the WRRQ is neglected by a gate 104 and the RDRQ is neglected by gates 106 and 105. Similarly, if the WRRQ is issued, the RDRQ is neglected. In this manner, a priority order determination circuit 109 determines the processing to be next carried out.
On the other hand, a refresh counter 110 counts by a refresh clock (REF CLK) generated by the timing generator 108. The REF CLK generates the refresh clock at the same period as the RQSPL. When the refresh counter 110 counts up to a predetermined count (refresh time), a FF 111 is reset. The output of the FF 111 is the refresh request (REFRQ).
In FIG. 3, since the REQRQ is fixed to the highest priority, it is processed at the highest priority whatever other requests are. The output of the FF 101 is actually a refresh execution request signal (REFEX) and the timing generator 108 responds to the REFEX to carry out the refreshing by changing row data address signal (RAS), column data address signal (CAS) and write enable (WE) signal. The RAS, CAS and WE are collectively called a DRAM control signal. Numeral 113 denotes a memory circuit comprising a DRAM. At the end of the refreshing, the timing generator 108 generates a refresh request release signal (REFCLR) to reset the FF 111.
Write release signal (WRCLR) and read release signal (RDCLR) are also generated each time the writing and reading are carried out, respectively, and they are sent to a CPU (not shown) to release the requests. When the request is not accepted because of a higher priority request and it is not executed, the request release signal is not issued and the request remains.
The operation of the prior art circuit of FIG. 3 has thus been described. In the DRAM, the refreshing is essential and positively done by imparting the highest priority to the RERRQ. However, the refreshing has no direct connection to the data processing itself. If a lower priority is imparted to the refresh request than other requests, the refreshing has to wait each time the refresh request is issued. This is not appropriate for the prior art fixed priority order system.
In an image memory of a high speed facsimile machine which stores compressed image information, the writing of the image memory into the memory, which should be faster than the refreshing, must frequently wait. As a result, the processing speed of the machine decreases.
When a memory of a large capacity is to be constructed, a RAM is usually used for a memory whose major requirements are high speed and random access capability. In such a large capacity memory, a power consumption necessarily increases. Thus, in a stand-by state where the apparatus is not in operation, a main power supply is turned off to reduce the stand-by power consumption.
However, in a conventional RAM, stored information is erased when the power supply is turned off, except for a special non-volatile RAM. Thus, two systems of power supply are used so that a memory portion which stores important data and programs which are not to be extinguished is powered by a normally-ON power supply and another memory portion is powered by a power supply which is turned on only during the operation period. However, this requires a complex power supply configuration and an increase in overall cost.
In a recently developed image processing apparatus for processing image data, the memory capacity is large compared to a scale of the overall system. Thus, the proportion of power consumption by the memory is high in many cases. In such an apparatus, it is difficult from the space standpoint to have two channels of the power supply or the proportion of cost for the power supply is high.
When data is to be transferred by operating the memory at a high speed by a memory control circuit, it is necessary to drive the memory at a high speed. As a result, a timing condition to the drive waveform is severe. There is no timing margin for the control of data bus and errors are apt to be produced.
In prior art memory control circuits, only an address counter for counting the address, reset means for the address counter and read means for reading out the address from the address counter are provided. In such a circuit, when data is to be read while a large amount of data such as image information are temporarily stored, it is necessary to reset the address counter or stop writing when the memory becomes full while the address in the address counter is always monitored by a central processing unit (CPU) in order to prevent the data from being destroyed.
When the above processing is carried out without occupying a memory area in which unprocessed image data are stored, supervision by the CPU is also required. This eventually increases the workload of the CPU. As a result, the CPU cannot process its intended jobs at a high speed.